1. Field of the Invention
The present invention relates to electronics, and, in particular, to phase-locked loops.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates a periodic output signal that has a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL, which is described in Floyd M. Gardner, "Charge-Pump Phase-Lock Loops" IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference.
FIG. 1 shows a block diagram of a conventional charge-pump phase-locked loop 100. Phase detector (PD) 102 compares the phase .theta..sub.IN of the input signal F.sub.IN to the phase .theta..sub.OUT of the feedback signal F.sub.OUT and generates an error signal: either an UP signal U (when .theta..sub.IN leads .theta..sub.OUT) or a DOWN signal D (when .theta..sup.OUT leads .theta..sub.IN), where the width of the error signal pulse indicates the magnitude of the difference between .theta..sub.IN and .theta..sub.OUT.
Charge pump 104 generates an amount of charge equivalent to the error signal (either U or D) from PD 102. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the capacitors in loop filter 106. For purposes of this explanation, loop filter 106 has a relatively simple design, consisting of a capacitor C.sub.S in parallel with the series combination of a resistor R and a relatively large capacitor C.sub.L. As such, loop filter 106 operates as an integrator that accumulates the net charge from charge pump 104. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage V.sub.LF is applied to voltage-controlled oscillator (VCO) 108. A voltage-controlled oscillator is a device that generates a periodic output signal (F.sub.OUT in FIG. 1), whose frequency is a function of the VCO input voltage (V.sub.LF in FIG. 1). In addition to being the output signal from PLL 100, the VCO output signal F.sub.OUT is used as the feedback signal for the closed-loop PLL circuit.
Optional input and feedback dividers 110 and 112 may be are placed in the input and feedback paths, respectively, if the frequency of the output signal F.sub.OUT is to be either a fraction or a multiple of the frequency of the input signal F.sub.IN. If not, the input and feedback dividers can both be considered to apply factors of 1 to the input and feedback signals, respectively.
Due to the effect of the feedback path in PLL 100, the steady-state output signal F.sub.OUT will have a fixed phase relationship with respect to the input signal F.sub.IN. Under ideal conditions, unless some phase offset is purposely added, the phases of the input and output signals in PLL 100 will be synchronized with zero offset. In reality, however, a phase-locked loop, such as PLL 100 of FIG. 1, will operate with some non-zero phase offset. One cause for such phase offset is a mismatch between the UP and DOWN currents generated by charge pump 104. This may be due to inherent imbalances within either the phase detector or the charge pump, or both. In the presence of an UP/DOWN current mismatch, the PLL feedback loop has to put a phase offset between the two inputs to PD 102 to generate UP/DOWN pulses that balance the mismatch in order to achieve a phase-locked condition. Under constant operating conditions (e.g., temperature and clock cycle), this particular type of phase offset is itself typically constant and is therefore referred to as static phase offset.
Since PLLs are widely used in clock distribution applications, avoidance of a phase difference between the input reference system clock and the PLL-generated output clock is desired. Any phase difference degrades system performance and can be catastrophic, especially at higher frequencies, where the period of the PLL's input and output signals are smaller, leaving very limited leeway between edges of the input and output signals.
Furthermore, a charge-pump phase-locked loop, such as PLL 100 of FIG. 1, might not be able to operate satisfactorily in high-frequency applications due to differences in the mobility of holes and electrons through the integrated circuitry (e.g., in a generic CMOS technology). In such cases, the charge pump will not be able to generate pump-up currents fast enough in response to the high-speed pulse signals from the phase detector. Possible solutions include using a pull-up resistor in the loop filter to make one integrator lossy or setting a current source in the charge pump open loop. Unfortunately, such solutions would only increase the magnitude of the static phase offset in the PLL.